Design of row decoder for redundant memory cell (SRAM)

Abstract

In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory array. The proposed circuit increases the yield and reliability with some loss in speed and overhead in terms of chip area. The circuit designed can test the design whenever a command to test is issued and it will detect and store the faults. Control Circuit designed, checks whether the given address of the memory operation is correct or not. If the address is faulty it replaces the faulty address with the spare address available in the chip. The existing control mechanism to replace faulty cell in a row replaces the cell bit by bit. But the design here instead of replacing the bit wise cells replaces the entire row containing the faulty cell. This architecture is more useful when there are more faulty cells in a single row. The row decoder is optimally implemented to reduce the time to access the data from memory. The operating voltage for the design is 3V. Layout, Simulation of testing circuit and redundant circuit with row decoder has been designed in CADENCE tool for .18μm technology. This Row decoder is working with 2.5GHz frequency.