Browsing by Author "Nagchoudhuri, Dipankar"

Now showing items 1-20 of 26

    • 6bit 800 MHz time-interleaved analog to digital converter based on successive approximation in 65 nm standard CMOS process 

      Salimath, Arunkumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      High-speed analog-to-digital converters (ADCs) with resolutions of 6 bits find wide application in instrumentation, wireless systems, optical communication. This dissertation presents a 6 bit, 8 channel Time-Interleaved ...

    • Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system 

      Pathak, Abhishek (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      Today’s high speed digital and analog VLSI systems are operating in GHz frequency range. With high switching rate of the devices, power distribution network (PDN) impedance causes ripples in power supply. If PDN is not ...

    • Architecture design for preliminary ECG analysis system using new DFT based analysis technique 

      Chaurey, Vasudha (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      This thesis proposes a hardware architecture of an ASIC for a portable ECG analysis system. The device is meant to record and analyze ECG signals in real time so as to detect the presence of abnormalities. In order to ...

    • Built-in self test architecture for mixed signal systems 

      Jain, Mahavir Rajmal (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ...

    • Column decoder for memory redundant cell array 

      Nahar, Pinky (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy ...

    • Design of a low power, high speed MAC unit 

      Mohanty, Swaprakash (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      MAC operation is the main computational kernel in any digital signal processing architectures. MAC consumes nearly 2/3 portion of total power dissipated in a DSP block. This thesis deals with the design of a low power, ...

    • Design of low power and high speed decoder for 1MB memory 

      Gupta, Punam Sen (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with ...

    • Design of low voltage high performance voltage controlled oscillator 

      Ramesh, R (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback ...

    • Design of row decoder for redundant memory cell (SRAM) 

      Mishra, Ashwini Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...

    • Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier 

      Ranjith, P (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. ...

    • Efficient ASIC implementation of advanced encryption standard 

      Joshi, Ashwini Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In spite of the many defense techniques, software vulnerabilities like buffer overflow, format string vulnerability and integer vulnerability is still exploited by attackers. These software vulnerabilities arise due to ...

    • Efficient scan-based BIST scheme for low heat dissipation and reduced test application time 

      Shah, Malav (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      Switching activity during test application can be significantly higher than that during normal circuit operation in many circuits. This is due to the fact that the correlation between consecutive test vectors is significantly ...

    • Extremely low voltage operational amplifier design with rail-to-rail input common mode range 

      Malviya, Yogesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      Increasing trends towards battery operated systems demand circuits to be designed at low voltages. Low voltage operation severely limits the operational amplifier as a voltage buffer as the input common mode range available ...

    • High-speed 512-point FFT single-chip processor architecture 

      Sinha, Ajay Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      This thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number ...

    • Integrated chaos generator 

      Shah, Nishit H. (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      With the explosion of information, the need to cater to the demands of increased number of users is of paramount importance. Spread Spectrum Technique used in wideband communications have proved to utilize the limited ...

    • Investigation of low power design of left-right leap frog array multiplier 

      Sankar, K. Ravi (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      This thesis addresses the Low Power design of 12 bit LRLFAM at the Layout, circuit and logic levels. A new Low power Booth-Recoder (BR), and Multiplexer based partial product generated are designed using pass-Transistor ...

    • Low power and high speed sample and hold circuit 

      Trivedi, Ronak (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      In this thesis work the design of a high speed and low power CMOS sample and hold circuit as a front-end block of pipelined analog-to-digital converter is described. The circuit consists of bottom-plate sampling with ...

    • Low power BIST architecture for fast multiplier embedded core 

      Vij, Aditya (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores. In this work, ...

    • Low power high speed amplifier design 

      Bensal, Jitendra Babu (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      The operational amplifier (op-amp) is one of the important component in analog to digital converters. The power consumption of these converters mostly depend on the op-amps used. The accuracy and speed performance of analog ...

    • Low power improved full scan BIST 

      Parashar, Umesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that ...