Now showing items 1-3 of 3

    • Design of row decoder for redundant memory cell (SRAM) 

      Mishra, Ashwini Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...
    • High speed sample and hold circuit design 

      Dwivedi, Varun Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
    • Reduction of power using innovative Clock Gating and Multi Vth techniques in digital design 

      Sharma, Dushyant Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
      Low power is one of the most important issues in today’s ASIC (Application Specific Integrated Circuit) design. As the transistors scale down, power density becomes high and there is immediate need of reduction in power. ...