Now showing items 1-20 of 26

    • 10-bit high speed high SFDR current steering DAC 

      Bapodra, Dhairya B. (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      The Thesis presents an attempt to design a 10-bit High Speed High SFDR Current Steering DAC with a simple and different approach. Most of earlier approaches contain complex design and bulky unary portion. Here an approach ...
    • Adaptive analog line driver using digital tuning 

      Singh, Harsh Verdhan (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Transmission lines are widely used for transmitting electrical signals. A line driver is a part of the analog front-end transmitter for wired line communication. It is a voltage buffer that provides the necessary output ...
    • Area reduction in 8 bit binary DAC using current multiplication 

      Upraity, Maitry (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      A proposed current multiplication technique is applied on 8 bit binary current steering Digital-to -Analog Converters with LSB 150 μA, to reduce area. MSB 1 and MSB 2 current are first kept half to reduce area and then ...
    • Asynchronous analog to digital converter 

      Patel, Vidyut A. (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      Nowadays, asynchronous systems are becoming more popular for low power applications. Asynchronous Systems help to reduce metastability errors and clock skew errors. This thesis is about an asynchronous analog to digital ...
    • Auto tuning circuit for continuous time filters 

      Nadimenti, Rakesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      This thesis presents the design of auto tuning circuit for continuous time filters and is designed for applications that require high linearity and moderate precision. This scheme is used to improve tuning range of 50% and ...
    • Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch 

      Chevella, Subhash (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the ...
    • CMOS RFIC mixer design 

      Gupta, Mukesh (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      A CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local ...
    • Column decoder for memory redundant cell array 

      Nahar, Pinky (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy ...
    • Design of a CMOS variable gain amplifier 

      Verma, Vivek (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new ...
    • Design of a high speed I/O buffer 

      Rathore, Akhil (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. ...
    • Design of low power and high speed decoder for 1MB memory 

      Gupta, Punam Sen (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with ...
    • Design of low voltage high performance voltage controlled oscillator 

      Ramesh, R (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In this thesis an ultra low voltage differential capacitive feedback VCO is being proposed .The VCO operates at very low supply voltage of 0.6V.The VCO uses techniques like Forward Body Bias (FBB), and capacitive feedback ...
    • Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors 

      Sesha Sai, Aduru Venkata Raghava (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor ...
    • Design of row decoder for redundant memory cell (SRAM) 

      Mishra, Ashwini Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...
    • Design of the analog front end circuit for X-ray detectors 

      Roy, Subhash Chandra (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      The Thesis presents a novel idea to efficiently read out the value corresponding to incident X-Ray, from X-Ray sensor. A system level solution has been proposed which is unique in itself in terms of approach. A simple ...
    • Design of the high speed, high accuracy and low power current comparators 

      Chasta, Neeraj Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current ...
    • Design of voltage reference circuits 

      Panchal, Bhavi (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      Shrinking device dimensions in advancing CMOS technologies require lower supply voltages to ensure device reliability. As a result, analog circuit designers are faced with many challenges in finding new ways to build analog ...
    • Fault diagnosis algorithm for a flash ADC using oscillation based testing technique 

      Aggarwal, Divya (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising ...
    • High speed sample and hold circuit design 

      Dwivedi, Varun Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
    • Investigation of low power design of left-right leap frog array multiplier 

      Sankar, K. Ravi (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      This thesis addresses the Low Power design of 12 bit LRLFAM at the Layout, circuit and logic levels. A new Low power Booth-Recoder (BR), and Multiplexer based partial product generated are designed using pass-Transistor ...