Now showing items 1-4 of 4

    • D-latch based low power memory design 

      Tripathi, Saurabh (Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
      Low power consumption is the main attraction of the digital circuit design in the Sub threshold region of operation. In this region of operation less energy is consumed for active operation and less leakage power is ...
    • Design of low power and high speed decoder for 1MB memory 

      Gupta, Punam Sen (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with ...
    • Distributed caching mechanism for video on demand on the Internet 

      Soni, Maulik (Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
      Video on Demand applications in the Internet are delay sensitive and highly resource intensive applications. Such applications require streaming of large video files in a time bound manner. Because large volume in terms ...
    • Hot and cold data identification using query aware hybrid partitioning 

      Kanwar, Jai Jai (Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
      The price of main memory is reducing with time, which helps to store huge amount of data in the memory. OLTP applications have large database size. It is observed that some applications exhibit skewed access pattern i.e. ...