Now showing items 1-8 of 8

    • Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system 

      Pathak, Abhishek (Dhirubhai Ambani Institute of Information and Communication Technology, 2009)
      Today’s high speed digital and analog VLSI systems are operating in GHz frequency range. With high switching rate of the devices, power distribution network (PDN) impedance causes ripples in power supply. If PDN is not ...
    • Design methodology for architecting application specific instruction set processor 

      Desai, Meghana (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      Application Specific Instruction-set Processors (ASIP), also referred as extensible processors, represent the state-of-the-art microprocessor architecture. ASIPs are practically leading towards the realization of ...
    • High-speed 512-point FFT single-chip processor architecture 

      Sinha, Ajay Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      This thesis present a fully parallel novel fixed point 16-bit word width 512 point FFT processor architecture. The 512 point FFT is realized by decomposing it into three 8 point FFT units. This approach reduces the number ...
    • Lifetime analysis of wireless sensor nodes using queuing models 

      Anand, Guneshwar (Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
      Prolonging the lifetime of wireless sensor networks (WSN) is one of the key issues for wireless sensor network applications. For increasing the lifetime of network, each node should conserve its energy. Sensor nodes consume ...
    • Low power microprocessor design 

      Bhatt, Vishal (Dhirubhai Ambani Institute of Information and Communication Technology, 2007)
      This research work tries to reduce the power consumption of a processor with signal processing features. For low power design, focus is on developing ‘Low power synthesizable Register File’, as the initial study shows that ...
    • Low power SRAM design 

      Bambhaniya, Prashant (Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
      In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power ...
    • Low-power multi-ported register file for digital signal processors 

      Aguduri, Nagamanoj Kumar (Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
      Digital Signal Processors (DSPs) also come under the category of processors in which Multi-ported register files can find their applications widely. Most of the DSP applications do not benefit from further speeding-up after ...
    • Single electron transistor based 4-bit ALU design, simulation and optimization 

      Joshi, Rathin K. (Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
      Objective of this thesis work is to create and optimize Single Electron Transistor(SET) based digital design. In present era for electronics, alternative approaches, other than CMOS (like SET,finFET,quantom dot) are much ...