Browsing by Subject "Very large scale integration"
Now showing items 1-14 of 14
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Analysis and modeling of power distribution network and decoupling network design strategies for high speed digital and analog VLSI system
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)Today’s high speed digital and analog VLSI systems are operating in GHz frequency range. With high switching rate of the devices, power distribution network (PDN) impedance causes ripples in power supply. If PDN is not ... -
Built-in self test architecture for mixed signal systems
(Dhirubhai Ambani Institute of Information and Communication Technology, 2009)Built-in self test architecture or BIST as we call them, are the necessity of time since the shrinking sizes of component on-chip with advance in IC technology are making it BIST artistries are being rapidly developed and ... -
CTS and CCOpt metodology's to achieve low skew-low power clock.
(Dhirubhai Ambani Institute of Information and Communication Technology, 2013)In synchronous VLSI chips, clock distribution network plays an important role. The quality of clock network mainly effects the performance of the chip, because the speed of data transfer depends on clock signal. Achieving ... -
Design of a CMOS variable gain amplifier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)In advanced CMOS technologies as device dimensions are decreasing, requirement for lower supply voltages are increasing to make certain device reliability. So, challenges for analog circuit designers are to discover new ... -
Design of low power and high speed decoder for 1MB memory
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)Technology scaling is accompanied by rise in leakage power dissipation. This thesis proposes a voltage controllable circuit in the feedback path of the decoder, which drastically reduces the standby leakage current with ... -
Design of low-voltage, low-power, wide-band CMOS LC VCO using active inductors
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)In this thesis the design of low-voltage, low-power, wide-band CMOS LC VCO using active inductor has been proposed. The oscillator is based upon the classic LC-tuned negative-resistance topology, with a novel active inductor ... -
Design of the high speed, high accuracy and low power current comparators
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”. A current ... -
Designing of an efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry save multiplier
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)This thesis presents a novel four-phase power clock generator for low power adiabatic logic without using inductors. The power clock generator is designed using current mirror arrangement of PMOS and NMOS transistors. ... -
Efficient scan-based BIST scheme for low heat dissipation and reduced test application time
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)Switching activity during test application can be significantly higher than that during normal circuit operation in many circuits. This is due to the fact that the correlation between consecutive test vectors is significantly ... -
High speed sample and hold circuit design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ... -
Investigating into a light-weight reconfigurable VLSI architecture for biomedical signal processing applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2019)The Body Sensor Network systems consist of signal acquisition and processing blocks along with Power Management Unit and radio transmission capabilities. The high power consumption of the radio transmission is often ... -
Low power improved full scan BIST
(Dhirubhai Ambani Institute of Information and Communication Technology, 2007)Low power testing of VLSI circuits has recently become an area of concern due to yield and reliability problems. Past research on low power testing has shown that, switching activity and test time are the main factors that ... -
Low power SRAM design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)In the past, power dissipation was not constraining factor because of device density and operating frequency was low enough. But nowadays due to increased integration and operating frequency of integrated circuits, power ... -
Study of the effectiveness of various low power techniques on sequential and combinational gate dominated designs
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)In last decade, the technological advancement is seen in semiconductor field like never before. The need for low power has caused a major paradigm shift where power dissipation has become as important consideration as ...