Comparative study of performance parameter of Phase-Locked Loops in CNTFET and CMOS technologies at deep sub-micron level

Abstract

We discuss about the improving performance of PLL using CNTFETs with circuit architecture along with its simulation results. There is no such work presented before which illustrate the complete PLL design using CNTFET. The schematic of simulation circuit is based on conventional design of Phase Locked Loop. The model used is virtual source CNTFET model which describes enhancement mode, unipolar MOS transistors with semiconducting single walled CNT as channels. The model is based on a quasi-ballistic transport and embraces a precise explanation of the capacitor network in a CNTFET. All the circuit design and simulation performed in Cadence Virtuoso and general idea of layout taken from different references to get an approximate idea of area occupied by the PLL. As compared to PLL using MOSFET at 45nm, 16nm CNTFET based PLL gives approximately upto 33% more frequency signal at output, and consumes upto 90% less power and area.