ASIC Chip Design For Agriculture Application

Abstract

This paper presents an application specific integrated circuit (ASIC) implementation suitable for agriculture applications, which employ RISC-V as a digital processing unit and the sensor interfacing circuits. The motivation is early plant disease detection and providing control measures to improve yield. The design consists of three sensors for collecting the temperature, humidity, and wetness of crops. The design targets an edge computing application where data is processed and analyzed closer to the point where it is obtained. Because of this, the latency and the required bandwidth are reduced considerably. The design of analog circuits is done using the specifications obtained from the sensors. The data obtained can be processed with the computing device to extract information and take desired actions. The RTL based design of a processor is implemented using Verilog HDL. Logic equivalence is verified using Xilinx ISE. Physical realizations of the design are obtained using RTL to GDSII design flow. The analog design consists of a unity gain buffer, sample and holds circuit, and flash type ADC. We have tested our ASICs with AMS verification methodology using Cadence CAD tools. The area of the designed RISC core is 50927 um2 , the criticalpath delay is 361 ps, and the power consumption is 420 uW after the placement and route stage. The designed analog ASIC contains all the signal processing components, and the combined length of all the routed layers comes out to be 23358 um. Vertical length is almost 70%, and the remaining is Horizontal length. The total area of the analog ASIC is 2.366 mm2.