Neural Network Architectures for Integrated Circuits
dc.contributor.advisor | Maiti, Tapas Kumar | |
dc.contributor.author | Nagrani, Khyati | |
dc.date.accessioned | 2024-08-22T05:21:18Z | |
dc.date.available | 2024-08-22T05:21:18Z | |
dc.date.issued | 2023 | |
dc.identifier.citation | Nagrani, Khyati (2023). Neural Network Architectures for Integrated Circuits. Dhirubhai Ambani Institute of Information and Communication Technology. vii, 61 p. (Acc. # T01117). | |
dc.identifier.uri | http://drsr.daiict.ac.in//handle/123456789/1176 | |
dc.description.abstract | This thesis presents the architecture design and implementation of neural networks(NNs) for integrated circuit design. The architecture consists of adders,multipliers, and rectified linear unit (ReLU) blocks. Three architectures, namely,Single-In Single-Out (SISO), Multiple-In Single-Out (MISO), and Multiple-In Multiple-Out (MIMO) are developed. In neural networks, weight values are necessaryand they are supplied from a memory source. The weight values were preparedby training the NNs model on software. Finally, the SISO, MISO, and MIMOneural-networks were taped out. These architectures can be used for intelligentco-processor development. | |
dc.publisher | Dhirubhai Ambani Institute of Information and Communication Technology | |
dc.subject | Neural Network | |
dc.subject | Integrated Circuits | |
dc.subject | Architecture design | |
dc.subject | MIMO | |
dc.subject | MISO | |
dc.subject | SISO | |
dc.classification.ddc | 621.3815 NAG | |
dc.title | Neural Network Architectures for Integrated Circuits | |
dc.type | Dissertation | |
dc.degree | M. Tech | |
dc.student.id | 202111031 | |
dc.accession.number | T01117 |
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M Tech Dissertations [923]