Fault diagnosis algorithm for a flash ADC using oscillation based testing technique

Abstract

With the advent of system-on-a-chip (SoC) designs, the semiconductor industry wants to solve problems that constrain the coexistence of analog and digital cores on a single chip. The complexities of modern (SoC's), comprising of analog, digital and even Radio-Frequency (RF) blocks on a single chip, are surpassing all the previous limits. Merging so many different technologies poses new challenges, such as developing design and test methodologies capable of ensuring system performance and reliability for a reasonable design effort. Digital testing has developed in to a complete science in the last forty years, but analog and mixed-signal are still in its initial state. The lack of standard models and methodologies is worsening this situation.

This work addresses the problem of fault coverage in analog and mixed signal circuits and proposes a fault diagnosis algorithm using Oscillation based Testing Technique. Present calibration techniques compensate for deviations in the measured parameters and do not correct the faulty value, because the faulty value cannot be obtained. A fault diagnosis technique able to perform fault identification (obtain fault values) will lay the groundwork for the development of more effective calibration techniques. Analog to digital converter (ADC) is used as a test vehicle to demonstrate the capability of the proposed OBIST technique. This technique employ Oscillation frequency test data for fault location and identification of the analog components in the converter. In the flash ADC, a fault causes deviation of Oscillation frequency from the ideal one. Hence, it can be considered as a functional signature of the ADC and this property is employed for fault diagnosis. ADC's are virtually in all modern SoC's and hence are one of the most important modules in analog and mixed-signal designs. Here, we have 3-bit, 1 GHz CMOS Flash ADC, designed in 0.18 μm CMOS technology as a benchmark. The simulation results prove that this technique shows an excellent coverage of catastrophic as well as a good coverage of parametric faults, also the algorithm proposed locate the faults in resistive ladder and comparators. The area overhead is very less in this techniques and it works on the circuit speed so, lesser test time.