CMOS RFIC mixer design

Abstract

A CMOS RF (Radio Frequency) up/down conversion mixer results in a reasonable increase in transceiver integration and a reduction in cost. The design of mixers faces many compromises between conversion gain(GC), local oscillator (LO) power, linearity, noise figure (NF), port-to-port isolation, voltage scaling and power consumption. Mixer linearity is a very important parameter in transceiver design, because system linearity is often limited by the first down-conversion mixer due to a relatively large signal compared with that at the LNA input. Since active FET (Field Effect Transistor) mixers achieve conversion gain with lower LO power than their passive counterparts, the active CMOS single-balanced and double-balanced Gilbert mixers are commonly used in the CMOS transceiver design. Compared with the single-balanced counterpart, the double balanced mixer has better port-to- port isolation due to symmetrical architecture. The double-balanced mixer has a higher noise figure due to more noise generators. The overall Gilbert mixer linearity is controlled primarily by the transconductance stage if the LO-driven transistors act as good switches.

This report describes a Gilbert cell mixer with source degeneration for 900 MHz frequency. The circuit converts a 900 MHz RF signal directly to base band [IF (Intermediate frequency) 45 MHz] using an 855 MHz LO frequency. The mixer uses common source MOSFETs with inductive degeneration to convert the input RF voltage to a current. This current is then steered using a switching network composed of MOSFETs that is driven with the LO and a 180 degree phase-shifted version of the LO. Gilbert Mixer achieves gain through an active predriver [The V-I (voltage to current) converter]. This V-I converter is highly nonlinear; hence, the Gilbert Mixer distortion performance is worse. This thesis tries to propose a simple linearity improvement technique for Gilbert Cell Mixer by including an additional capacitor located in parallel with the intrinsic gate-source capacitor of the common source transconductance stage. Also, to reduce the flicker noise of the switching transistors which depends on the frequency and circuit capacitance at the common source node of the switching stage, a method is used to reduce this capacitance by adding an extra inductor that helps for simultaneously match low 1/f noise, high linearity and low NF at the expense of Conversion gain. The design is based upon the third order intermodulation distortion (IM3) and output current equations of MOSFETs and flicker noise equation when it is subjected to an ac input signal. The performance has been verified using Agilent’ Advanced Design System (ADS) simulations. The designed mixer has a voltage conversion gain of 15.804 dB, NFSSB of 6.565 dB, NFDSB=3.975 dB, IIP3 of -1.158 dBm, OIP3 USB of 14.699 dBm, OIP3 LSB of 14.646 dBm, LO to IF isolation of -27.532 dB, LO to RF isolation of -69.365 dB and RF to IF isolation of -56.554 dB for single ended RF Input.