Low drop-out (LDO) voltage regulator without off-chip capacitor

Abstract

Designing of Low Drop-Out Voltage Regulators (LDOs) operating without a large off-chip capacitor, having a very good transient response and maintaining the loop stability for full load current range in low supply voltage and low quiescent current environment is a challenging task. The present thesis work proposes a technique to achieve faster loop response during load transients while consuming very less quiescent current. The idea revolves around fast charging and discharging of the large equivalent capacitor at the gate of the pass transistor in response to fast load current transients. The extra circuitry added does not affect the working of main feedback loop in steady state conditions. The idea is inspired from the Nagraj’s idea of achieving high slew rate in operational amplifier which uses an auxiliary circuit to produce large currents in one of the two switching transistors, one for charging and other for discharging the slew rate limiting capacitor in the circuit. A common source amplifier (having i/p v/s o/p characteristic which closely resembles a digital inverter) followed by the large, normally off switching transistor is used here to overcome the slew rate limitation at the gate of pass transistor.