Design and implementation of 128-point fixed point streaming FFT processor for OFDM based communication system

Abstract

Fast Fourier Transform (FFT) processors are today one of the most important blocks in communication systems. They are used in every communication system from broadband to 3G and digital TV to Radio LANs. This master’s thesis project deals with the pipelined, radix-2 algorithmic exploration and the hardware solution for the FFT processor with the FFT size of 2N points, the selection of the scaling schemes based on application requirement is discussed. The designed architecture is functionally verified in Simulink® and the Xilinx® ISE simulator. How to encapsulate the C++ coded algorithms or functions into the Simulink. This FFT processor is used in OFDM based BPSK modulated communication system for the WHD WVAN standard at the Low Rate Physical (LRP) lay. This thesis project presents the design of the 128 point fixed–point F streaming processor. The final architecture used is the SDF (single path with delay feedback) that implements the radix-2 FFT algorithm. Since the FFT processor can’t be used standalone, so in this thesis it is employed in an OFDM Transmitter and the performance is measured for SNR over a range of PAPRs. The goal of this report is to outline the knowledge gained during the master’s thesis project, to describe a design methodology for the fixed point pipelined FFT processors, the scaling choices and how to encapsulate the existing C code into the Simulink environment to measure the performance of fixed-point systems.