Single ended sense amplifier for DRAM

Abstract

Today design of eDRAM is facing more challenges as the technology node is scaling down every year. Supply Voltage is also scaling down in accordance with the technology. Thus, charge on the bitlines, to sense is also decreasing, which is prominent to be affected by noise. Hierarchical based sense amplifier is used to eliminate this effect. This structure reduces the bitline capacitance to 6fF in 90nm technology node. As the ratio of the cell capacitance and the bitline capacitance is increased to 1:10 to 3.3:1 (approx.) which increased the sensing voltage to 600-750mV. Here, sense amplifier can sense the bitline without using the dummy bitlines in the structure i.e., single ended sense amplifier. It eliminates the complex bitline and dummy cell structure from the DRAM array. Cell bitline (Local Bitline LBL) is charged and discharged through the Primary Sense Amplifier (PSA) which is done by utilizing the Secondary Sense Amplifier (SSA). This Secondary Sense Amplifier is connected to the Global Bitline (GBL) through Tertiary Sense Amplifier. Activation of TSA is also not required in the refreshing cycle. Here charge transfer rate from the cell to GBL is also increased by using hierarchical based sense amplifier. Its latency of charge transfer is 1.4ns with typical overall cycle is 2ns. Present hierarchical based amplifier is also cost lower than the other hierarchical based sense amplifiers for eDRAM.