Low-power multi-ported register file for digital signal processors

Abstract

Digital Signal Processors (DSPs) also come under the category of processors in which Multi-ported register files can find their applications widely. Most of the DSP applications do not benefit from further speeding-up after achieving certain speed. This thesis involves in building a multi-ported register file that takes advantage of loose speed-up requirements of DSPs to reduce the power consumption. However, this can also be used in any processor which requires multiple data accesses without requiring high-end performance. A 10 read, 6 write ported 64-entry 64-bit register file is designed using combinations of techniques proposed in various earlier research works. We propose some improvements to this design in order to still lessen the power consumption. The designed Register file operates at a frequency of 250 MHz and at a power supply of 1 V. The circuits are simulated using 90nm technology. The simulation results show that this design consumes 0.00226 mW/MHz-port.