Design and layout of single bit per stage pipelined ADC

Abstract

The concept of pipe-lining, often used in digital circuits, can also be applied in the analog domain. It helps to achieve higher speed where several operations must be performed serially. In this work, pipe-lining is employed to create the analog-to-digital converter. The architecture consists of N stages, each including a sample and hold circuit, an ADC, a DAC, a sub tractor and possibly an amplifier. In actual implementation we combine two or more of these functions in one circuit. By pipe-lining, in the converter an optimization can be obtained between maximum sampling clock and the speed of the circuits used. The layout of simulated pipe-lined ADC has been created and parasitic have been extracted. Rigorous pre-layout and post-layout simulations have been done and obtained results are analyzed. The single bit per stage pipe-lined ADC has been implemented in UMC 180nm technology and simulated in Cadence Virtuoso Environment.