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Realization of FPGA based digital controller
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Field Programmable Gate Array (FPGA) can be used to enhance the efficiency and the flexibility of digital controller. FPGA implementation of digital controllers leads to real time realizations with small size and high ...
Implementation of high speed serial communication blocks
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Serial communication is widely being used from PCs to handheld mobile phones due to very less hardware, low cost, easier design process in comparison to parallel communication. For bit by bit, reliable transmission and ...
Implementation of different branch prediction schemes on FabScalar generated superscalar processor
(Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
Performance of modern pipeline processor depends on steady flow of useful instruction for processing. Branch instruction in the program disrupts the sequential flow of instruction by presenting multiple paths through which ...
Migration in initial and dynamic virtual machine placement algorithms
(Dhirubhai Ambani Institute of Information and Communication Technology, 2013)
Cloud computing provides a computing platform for the users to meet their demands in an efficient way. Virtualization technologies are used in the clouds to aid the efficient usage of hardware. Virtual machines are utilized ...
High Performance Computing
(Dhirubhai Ambani Institute of Information and Communication Technology, 2016)
Technology today has evolved from the Mainframe computers to laptops to small and smart handheld devices. These smart end devices are accompanied with extremely robust ARM 64-bit processors which are a perfect blend of ...
Design and Implementation of Low Power Superscalar Processors
(Dhirubhai Ambani Institute of Information and Communication Technology, 2018)
This thesis presents an 8-stage low power Superscalar processor. Since there has come an upper limit on the frequency that a single core inline processor can provide, to improve performance we need to exploit concepts like ...