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Analysis of charge injection in a MOS analog switch with impedance on source side
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Turning off of a transistor introduces error voltage at the output of Sample and Hold circuits
which are the key components of Analog to Digital Converters (ADCs) and hence limits their
accuracy of performance in high ...
Capacitor mismatch in switched capacitor circuits, techniques to minimize mismatch
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
This thesis about the designing of capacitive mismatch insensitive switched capacitor amplifier for analog to digital converters (ADC). The accuracy of the conversion is an important factor. The accuracy depends upon the ...
Design and layout of single bit per stage pipelined ADC
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
The concept of pipe-lining, often used in digital circuits, can also be applied in the analog domain. It helps to achieve higher speed where several operations must be performed serially. In this work, pipe-lining is ...
High speed, low offset voltage cmos comparator
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is ...
High speed sample and hold circuit design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
High-performance low-voltage current mirror design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are ...
Novel 7T SRAM cell design for low power cache applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Scaling in integrated circuit technology directly paves way to increased package density,
thereby increasing onchip power. With continuous scaling, low power design techniques
results in efficient use of silicon die. ...
Single ended sense amplifier for DRAM
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
Today design of eDRAM is facing more challenges as the technology node is scaling
down every year. Supply Voltage is also scaling down in accordance with the technology. Thus, charge on the bitlines, to sense is also ...