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Statistical delay modeling and analysis for system on chip
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
It is seen that designing using conventional methodologies in Deep Sub Micron geometries, at times, ends up in very pessimistic design and less yield. This is because, today’s tools don’t consider statistical variation of ...
Low power BIST architecture for fast multiplier embedded core
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
A typical core is deeply embedded in the chip of a system so that direct access to its input/output is not possible. Built in self test (BIST) structures are excellent solutions for testing embedded cores.
In this work, ...
Efficient scan-based BIST scheme for low heat dissipation and reduced test application time
(Dhirubhai Ambani Institute of Information and Communication Technology, 2006)
Switching activity during test application can be significantly higher than that during normal circuit operation in many circuits. This is due to the fact that the correlation between consecutive test vectors is significantly ...