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Design of row decoder for redundant memory cell (SRAM)
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...
Reduction of power using innovative Clock Gating and Multi Vth techniques in digital design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Low power is one of the most important issues in today’s ASIC (Application Specific
Integrated Circuit) design. As the transistors scale down, power density becomes high and
there is immediate need of reduction in power. ...