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    Agrawal, Jatin (1)
    SubjectFPGA Implementation (1)Resolution Improvement Technique (1)Ring Delay Line (1)... View MoreDate Issued2017 (1)Has File(s)No (1)

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    Design of Low Power Time-to-Digital Converter in 0.18?m CMOS 

    Agrawal, Jatin (Dhirubhai Ambani Institute of Information and Communication Technology, 2017)
    A full custom, all-digital, low power Time-to-Digital Converter (TDC) based on a Time-based Analog to Digital Converter (TAD) is presented. The proposed architecture contains a 20-bit ripple counter, 16-bit latch, an ...

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