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Design of row decoder for redundant memory cell (SRAM)
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...
High speed sample and hold circuit design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...