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HDL implementation of associative memory based instruction predictor for power reduction
(Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
Now a days, power consumption in digital integrated circuits/systems is a major issue. The goal here is to reduce power consumption, by assuming the circuit is divided in different power consuming modules, observing their ...
HDL implementation and study of ANN architecture mapping onto multiple processing nodes
(Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
A general methodology has implemented on several Processing Nodes (PN) to be connected to form an Artificial Neural Network (ANN). This design has multiple Activation functions on the same architecture which makes it ...
HDL implementation of a node of bayesian polytree interface
(Dhirubhai Ambani Institute of Information and Communication Technology, 2014)
In this thesis, we have particularly focussed on the aspects of the hardware implementation of the Bayesian inference framework within the George and Hawkins’ model. This framework is based on Judea Pearl’s belief propagation. ...