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Design of a high speed I/O buffer
(Dhirubhai Ambani Institute of Information and Communication Technology, 2008)
In high speed serial transmission of data, output buffer creates the bottleneck. Current Mode Logic (CML) buffers have gained wide acceptance in most high speed serial interfaces as they reach speed of the order of Gbp/s. ...
High speed sample and hold circuit design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Sampling of the time-varying input signal is the first step in any type of Analog to Digital (A/D) conversion. For Low Power and high-speed A/D converter, a high-performance Sample and Hold (S/H) circuit is needed as its ...
High-performance low-voltage current mirror design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Design of high precision analog circuits requires accounting for the mismatch between nominally identical transistors. In this work, errors affecting CMOS current mirrors due to mismatch between identical transistors are ...