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Column decoder for memory redundant cell array
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
As the semiconductor technology advances, the yield of memory chip is reducing. The cause of yield degradation is errors in manufacturing process associated with tight geometries. The thesis work proposes a redundancy ...
Design of row decoder for redundant memory cell (SRAM)
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...