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Now showing items 11-20 of 26
Design and layout of single bit per stage pipelined ADC
(Dhirubhai Ambani Institute of Information and Communication Technology, 2011)
The concept of pipe-lining, often used in digital circuits, can also be applied in the analog domain. It helps to achieve higher speed where several operations must be performed serially. In this work, pipe-lining is ...
Design of a novel high linearity down conversion mixer for GSM band applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Double balanced Gilbert cell mixer (GCM) is the mostly used kind of mixer as it provides
conversion gain and has port to port isolation. This mixer lacks in linearity and noise figure
which are to be taken care in designing ...
Design of row decoder for redundant memory cell (SRAM)
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
In the modern technology, the error occurring in memory circuits has increased and the yield of manufacturing has reduced. In order to solve these problems, this thesis proposed a redundancy circuit for faulty row in memory ...
Design of the high speed, high accuracy and low power current comparators
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
Comparators are non linear, decision making analog circuits, which find wide spread application in data converters, data transmission and others. Comparison can be done in terms of “Voltage” or “Current”.
A current ...
High speed, low offset voltage cmos comparator
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
The Analog to digital converters are the key interface blocks between the continuous time domain and the discrete-time digital domain. The performance of high-speed data conversion and digital communication interfaces is ...
Novel 7T SRAM cell design for low power cache applications
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Scaling in integrated circuit technology directly paves way to increased package density,
thereby increasing onchip power. With continuous scaling, low power design techniques
results in efficient use of silicon die. ...
Path planning of data mule using responsible short circuit with steiner points
(Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
We have studied the problem of data aggregation method in wireless sensor network
using the data mule. In data mule approach, Data mule is the mobile entity
which can collect the data from stationary sensor node in the ...
Reduction of power using innovative Clock Gating and Multi Vth techniques in digital design
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
Low power is one of the most important issues in today’s ASIC (Application Specific
Integrated Circuit) design. As the transistors scale down, power density becomes high and
there is immediate need of reduction in power. ...
Robust surface coverage using deterministic grid based deployment in wireless sensor networks
(Dhirubhai Ambani Institute of Information and Communication Technology, 2010)
The rapid progress in the field of wireless communication ans MEMS technology has made wireless sensor networks (WSN) possible. These networks may have low cost sensors deployed which are capable of sensing any activity ...
Single electron transistor based 4-bit ALU design, simulation and optimization
(Dhirubhai Ambani Institute of Information and Communication Technology, 2015)
Objective of this thesis work is to create and optimize Single Electron Transistor(SET)
based digital design. In present era for electronics, alternative approaches, other than
CMOS (like SET,finFET,quantom dot) are much ...