Search
Now showing items 1-1 of 1
Zero-aware 6T asymmetrical SRAM cell for low power cache application
(Dhirubhai Ambani Institute of Information and Communication Technology, 2012)
This thesis walks around the design and analysis of Static Random Access Memories (SRAMs), with optimization of power as center of attention In this dissertation work a novel architecture of 6T SRAM cell has been designed ...