Study of the effectiveness of various low power techniques on sequential and combinational gate dominated designs

Abstract

In last decade, the technological advancement is seen in semiconductor field like never before. The need for low power has caused a major paradigm shift where power dissipation has become as important consideration as performance and area. The size of the electronic equipments is getting smaller and smaller which requires smaller integrated circuits (ICs). Due to this the power consumption happens to be a major concern in developing the smaller ICs. The objective of the dissertation is to develop a low power digital design flow using Cadence® tools. This report discusses various strategies and methods for designing low power circuits and systems. It describes the many issues facing designers at various levels and presents some of the techniques that have been proposed to overcome these difficulties. To do this, particular RTL (Verilog code) is taken for some design. First various floorplans are tested on the design for better power number then using the same design, analysis on two different interconnect estimation model is done. Finally using the floorplan and interconnect estimation model analysis results low power implementation is done for the same design which is passed through various steps of digital design flow like synthesis, floor planning, placement, routing, and converted to GDSII (Graphic Database System) file format which can be directly sent to foundry. In low power implementation several techniques like clock gating, operand isolation, and multi Vt cells are used with some enhancement switches provided by the tool