| dc.description.abstract | The trend towards digital processing of analog signals in an increasing number of application fields has stimulated significant research efforts in the area of data converters implemented in CMOS technologies. Designing data converters for a given specification takes an unacceptably large amount of designer’s time. The primary objective of the work reported here is to map human (expert) knowledge into the implementation of an Analog to Digital Converter (ADC) design system to speed up the overall ADC design process.
This work presents a Geometric Programming(GP) based design automation of ADCs. This automation gives a design with minimum power dissipation while taking other specifications as constraints. GP is an optimization problem, whose accuracy depends on the accuracy of equations used in it. Since using a square law model for short channel transistors runs into large errors, we have used a new transistor model to increase the accuracy of GP. Among the data converters, the design of Successive Approximation Register (SAR) ADC and Pipelined ADC are presented in this work.
As the first step of designing ADCs, different types of comparator architectures, namely OpAmp based comparator, static latch based and dynamic latch based comparators are designed. Both static latch based and dynamic latch based comparators employ positive feedback. For getting an accurate delay model from a positively fed back latch, we have developed a large signal model.
Capacitor array digital to analog converters (DAC) are an integral part of ADCs. The performance of ADCs depend upon the performance of the DACs employed in it. Different switching schemes are employed to enhance the performance of the DAC. To get a better performance we have developed a novel capacitor array based DAC. In this architecture three unit capacitors re- places the Most Significant Bit(MSB) capacitor of the conventional DACs, which reduces the area, power dissipation and settling time. The novel DAC neither requires an additional reference voltage nor an additional switching circuit. The architecture is verified by drawing a layout and doing post layout simulations.
A GP based automation algorithm for SAR ADC is written in MATLAB. According to the given specifications, the algorithm chooses the sub-blocks and integrates it to get a required SAR ADC. SPICE simulation results of a single ended 12 bit 1 MS/s SAR ADC in a 0.8 µm CMOS technology employing the proposed automation shows that the ADC consumes 0.8 mW power and thus justifies the proposed methodology.
This work also presents a systematic approach to the design of a multi bit per stage pipelined ADC. An algorithm based on geometric programming using MATLAB tool is developed to design pipelined ADC. The proposed algorithm computes the required design variables in a predefined ADC topology, for a specified process technology. Design variables includes number of stages, number of bits per stages, capacitor sizes in multiplying DAC and transistor sizes and biasing voltages in residue amplifier. Two additional methods, namely capacitor scaling and gain error improvements are adopted to reduce the power further. Using the proposed approach a 14 bit, 30 MS/s pipelined ADC with 3 V as supply voltage is designed in CADENCE with 0.18 µm technology.
The contributions of this work are:
1. A more accurate large signal delay model is proposed for both static and dynamic latch based comparators.
2. A novel Capacitor Array based DAC is developed which reduces power, area, noise and settling time.
3. Automation algorithms each for SAR ADC and Pipelined ADC are proposed to design the ADC for the given specifications. | |
