| dc.description.abstract | Scaling the supply voltage below the threshold voltage leads to orders of magnitude energy savings but puts the limit on performance of the circuit. This strategy is used in the emerging embedded applications for the energy constrained
systems, wherein the performance requirements can be relaxed. For many applications like wireless sensor networks, where the energy dissipation is of prime concern rather than performance or clock speed we can scale down the supply voltage to low level. Due to this, there is a considerable amount of leakage power reduction. A typical Wireless sensor node consist mainly of transceiver, digital
logic and a sensor. In our envisaged node, the sensor node is believed to be consisting of Ultrawideband (UWB) transmitter, digital logic that is a custom made light weight microprocessor and a capacitive sensor.
Digital logic contains a custom processor/controller which can handle some standard algorithms. The idea is to make a full custom design for such microprocessor so that it offers low power/energy requirements compared to existing designs.
First of all, the standard cell library has to be obtained which will work with the optimum voltage supply and threshold voltage for minimum energy dissipation. The standard cell library consists of cells like 2-input NAND, NOR, XOR gate, an inverter, a D-flipflop. The work have also considered implementation of a full custom schematic using 0.18mm CMOS. | |
