Performance enhancement of a pipelined architecture using backup FF

Abstract

Commonly used devices like computers and mobile phones demand faster processors. These devices need to live up to the ever growing demand of consumers for performance. Special techniques like Pipelining and Superscalar Architecture increase the performance of processors at the cost of hardware. When using a pipelined architecture, the maximum frequency of operation and hence performance is limited by the longest path between two consecutive Flip Flops, also called the critical path. In designs where the critical path is rarely used, the frequency of operation can be safely increased by employing mechanisms that correct the error introduced if the critical path is taken. One such mechanism using Backup Flip Flop has been discussed and implemented in this dissertation. Problems like Metastability have been analyzed and resolved.