| dc.description.abstract | With increasing clock frequencies, power-aware computing has become a critical
concern in the VLSI design. One of the most effective and widely used method for
lowering the power is DVS (Dynamic Voltage Scaling), which is the basic idea behind
making low-power pipeline. Total power consumed by the system consists
of dynamic power and leakage power. They both depend on the supply voltage,
as they decrease with a decrement in supply voltage. But lower supply voltage
causes more delays at the gate level, as there is less amount of voltage to charge
the output capacitance of a gate. These delays can cause timing violations in the
critical path. So, if the supply voltage of the system could be reduced somehow
without affecting the overall functionality of the system, great power saving can
be achieved.
Usual DVS techniques need to have margin for process and temperature variations
or any local variations. These voltage margins make the design less efficient
in terms of power. Backup flip-flop can be used for the critical path, which operates
on the different clock, delayed by some specific amount of delay. It covers the
effect of voltage reduction as well as process and temperature variations with all
local variation effects, which can affect delay in any manner. If there is any error,
it needs to be corrected for a correct functionality of the system. Error correction
mechanism and the architectural overview of AES crypto-core is also discussed,
as it is the chosen design on which this concept would be implemented. Similar
concept has been successfully tried out on Alpha processor with satisfactory
result.
All the simulations shown are post-synthesis or post-route simulations so that
they reflect the approximated delays and timing checks of logical gates and interconnects.
Simulations and synthesis were performed using Cadence NC-Launch
and Encounter RTL Compiler respectively. ’Nangate Opencell Library’ with 45nm
technology was used for the synthesis. | |
