Design of an interrupt driven processor having deterministic exception response

Abstract

In recent times, we have seen an impressive growth of portable devices, audiovideobased multimedia products and wireless communication systems. To meetthe intensive computational requirements and complex real time functions, it hasbecome important to integrate traditional microprocessor with memories and peripheralson a single chip, which is known as System-on-Chip (SoC).For any SoC targeted for real time application, two most important things are:Low power and Deterministic response. This thesis is concentrated on a SoChaving a deterministic response to any external interrupt as well as having lowinterrupt latency. To achieve these goals, a module named Nested Vectored InterruptController (NVIC) was made for handling the interrupts. To maintain rightbalance between power and performance, a 3-stage pipelined processor with extensiblefeatures was designed. Other modules of SoC are connection control unitand stack memory. The Design of SoC is done using Verilog language. Synthesisis performed using Cadence RTL Compiler. �Nangate Opencell Slow Library�with 45nm technology is used for the synthesis