Power reduction schemes in an interrupt driven processor based SoC
In recent time, an impressive growth of personal computing devices like portabledesktops, multimedia products and wireless communication systems has beennoted. As the IoT industry has grown very fast, so is the need for low powerprocessor. When we talk about smart city or a smart room, the first thing is thatthe data will be coming from sensors. Processor operating on the sensor datamust be quick to respond and low power, so as to remove the havoc of replacingbattery. To meet the intensive computational requirements and complex real timefunctions, it has become important to integrate traditional microprocessor withmemories and peripherals on a single chip, which is known as System-on-Chip(SoC). For any SoC targeted for real time application, two most important thingsare: Power Management and Deterministic response.Power consumption consists of two parts: Dynamic Power and Leakage Power.Initially dynamic power was dominating in total power consumption but with thetechnology node shrinking and devices becoming smaller in size, leakage powerhas become dominant part of power consumption. There are various techniquesdevised for reducing leakage power. An interrupt driven three-stage processoris designed using verilog, where sensor data acts as interrupt and deterministicexception response is done with the help of a module named Nested VectoredInterrupt Controller (NVIC).In this thesis power optimization is done at system, architecture and technologylevels. The thesis is mainly concentrated on power shut off (PSO) techniquewhich is implemented at system level and is most effective to reduce the leakagepower. It includes shutting off modules in design which are going to be idlefor some time. With the increase in complexity of design, PSO implementationalso becomes difficult to implement. It is implemented using the Common PowerFormat (CPF) or Unified Power Format (UPF). Here, CPF has been used to implementPSO and is done at three different designs levels; on ALU, interrupt drivenprocessor and the System on Chip (SoC). Techniques like clock gating, avoidingcells and library of slow PVT are used to further reduce leakage power along withPSO.
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