Reconfigurable Interrupt Driven Low Power Processor Having Deterministic Response
"With the growth in number of portable devices and applications in variety,the computational complexities have increased many folds. With such increase in complexities, the computational requirement has also gone up. And the combination of computational complexities and requirements lead to high power consumption. In such a day and time of ever developing applications, we need a system that has the ability to achieve the computational complexity with lowest power possible. Hence we propose a system where a deterministic response is guaranteed along with the total power usage of the system as low as possible. For applications which have real time requirements, deterministic response and low power are two of the most important requirements. The thesis is aimed on building an SOC which gives a guaranteed response to any external interrupt that comes. An interrupt controller block, namely NVIS schedules these interrupts by the scheduling algorithm it houses. A 3 stage pipelined processor is developed to process interrupts. The processor is made low power by applying different low power techniques. A bus makes sure that frequency mismatch between the external modules and core doesn’t happen. The complete analysis is done using RTL Compiler tool with NanGate Open cell 45nm library as the default library."
- M Tech Dissertations