Design Of Variable Frequency Low Power Interrupt Driven Processor With Deterministic Response
"This thesis, presents a design for real-time, low power, interrupt driven processor to monitor ambulatory patients. To achieve low power goals, a power-aware algorithm is proposed for scheduling periodic and sporadic interrupt requests to the processor. The interrupt controller of the design is governed by an algorithm that can adapt to higher or lower frequency according to the input interrupts and also assures the completion of all hard deadlines. Firstly, the periodic interrupts are scheduled statically using an updated minimum laxity first algorithm and Pre-emption Thresholds Scheduling. The frequency is increased when any sporadic interrupt is encountered, to adjust the interrupt within the given deadline. The initial operational frequency is calculated as the minimum possible frequency which completes the deadline for all the periodic interrupts. Low power constraints are applied to make a low power processor that will handle the interrupt requests coming from the interrupt controller. A bus is also designed that transfers data between the processor and peripheral sensors running at different frequencies."
- M Tech Dissertations