ASIC Implementation of STBC MIMO-OFDM System
MetadataShow full item record
"Space-Time Block Coded Multiple-Input Multiple-Output (STBC MIMO) System in combination with Orthogonal Frequency Division Multiplexing (OFDM) System is one of the currently used wireless technology around the world. MIMO technology helps in increasing the channel capacity by transmitting multiple signals over multiple co-located antennas without any extra power and bandwidth requirement. Space-time coding is used with MIMO system in which multiple copies of a data stream is transmitted from multiple antennas to ensure that the signals received at the receiver are properly detected and decoded. It also helps in reducing the complexity of the receiver as no Channel State Information (CSI) is required at the transmitter side when STBC is employed in the design. OFDM is a multi-carrier modulation technique in which a data stream is divided into a large number of orthogonal sub-carriers which are transmitted in parallel. OFDM helps in dealing with multi-path fading problem, uses limited frequency spectrum efficiently and also tackles with the problem of ISI. So, the combination of STBC MIMO technology with OFDM presents a high-performance communication system with the high-speed data rate, greater reliability of data transmission and better quality of service. STBC MIMO-OFDM is currently being used in LTE, WIMAX, DVB, IEEE 802.11n and IEEE 802.11ac standards and advance version of MIMO i.e. Massive MIMO will be incorporated in upcoming 5G and Multiuser MIMO (MU-MIMO) will be used in IEEE 802.11 ax standard. In this thesis, a design of STBC MIMO-OFDM System is based on Verilog HDL and MATLAB program. The design is implemented using Radix-4 256 point FFT and QPSK modulation scheme with 2 2 antenna configuration in multi-path fading environment. The design is simulated using MATLAB with Modelsim and the performance of the system is evaluated based on BER for various inputs such as text and image. Further Front-end analysis of the system is done using Cadence RTL Compiler Tool. The design is optimized for achieving low power and small silicon area using various constraints and clock-gating technique."
- M Tech Dissertations