Design of Low Power Time-to-Digital Converter in 0.18?m CMOS
A full custom, all-digital, low power Time-to-Digital Converter (TDC) based on a Time-based Analog to Digital Converter (TAD) is presented. The proposed architecture contains a 20-bit ripple counter, 16-bit latch, an encoder, an edge detector and a Ring Delay Line (RDL) with appropriate control logic circuit. The TDC-IC core has an area of 0.026mm2 in 0.18?m CMOS that achieves resolution of 586.4ps/LSB and 201.8ps/LSB, power consumption of 32.5?W and 315.5?W, with the distance calculation up to 2949.4km and 1015.7km at 1V and 1.8V respectively,making it feasible for distance measurement in space applications.
- M Tech Dissertations