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dc.contributor.advisorPillutla, Laxminarayana
dc.contributor.advisorBhatt, Amit
dc.contributor.authorBhanushali, Artiben
dc.date.accessioned2018-05-17T09:29:59Z
dc.date.available2018-05-17T09:29:59Z
dc.date.issued2017
dc.identifier.citationArtiben Bhanushali(2017).Digital Implementation of Orthogonal Frequency Division Multiplexing.Dhirubhai Ambani Institute of Information and Communication Technology.x, 44 p.(Acc.No: T00674)
dc.identifier.urihttp://drsr.daiict.ac.in//handle/123456789/706
dc.description.abstract"OFDM (Orthogonal Frequency Division Multiplexing) is the most important part of 4G and 5G technology which is adopted by many standards because of its various advantages. In this thesis, firstly prototype of OFDM system is designed according to 802.11a standard in MATLAB to check its performance and then to implement the same in Verilog using Xilinx ISE 14.4 design suite. FFT (Fast Fourier Transform) and IFFT (Inverse Fast Fourier Transform) are the most complex part of the design which are implemented using radix-2 algorithm. For channel estimation, scattered pilot arrangement is used to insert pilots at regular period in OFDM frame. At receiver side, least-square estimation is used to estimate the channel’s impulse response at known pilot tones. The system analysis is done using MATLAB-Verilog co-simulation in which Verilog transmitter and receiver are connected with MATLAB channel using testbench to generate the text files. This files are used as connecting platform between MATLAB and Xilinx. Performance of channel estimation at different number of multipath is observed which shows that the combination of time interpolation followed by frequency interpolation performs better over only frequency interpolation. In later part, BER (bit error rate) vs. SNR (signal to noise ratio) is analyzed for different number of multipath. From graphs, it is clearly denoted that, BER performance improves with respect to increase in SNR. Finally, fixed point and floating point comparison is carried out which depicts that fixed point system implemented in Verilog performs almost similar to the floating point implementation done in MATLAB."
dc.publisherDhirubhai Ambani Institute of Information and Communication Technology
dc.subjectWireless Channels
dc.subjectBandwidth
dc.subjectOFDM
dc.subjectOrthogonal Frequency Division Multiplexing
dc.subjectMATLAB
dc.classification.ddc621.38216 BHA
dc.titleDigital implementation of orthogonal frequency division multiplexing
dc.typeDissertation
dc.degreeM.Tech.
dc.student.id201511037
dc.accession.numberT00674


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