Performance analysis of next generation graphene interconnects
MetadataShow full item record
The state-of-the-art development and subsequent miniaturization of technologiesin e-systems such as computers and digital communication systems, have led todensely and compactly placement of devices and interconnects in ICs. The incessantadvancements of technologies have necessitated a rapid increase in operatingfrequencies. At nanometer dimensions and advanced technology nodes, performanceof the overall VLSI system is critically dominated by on-chip interconnects.Interconnects perpetuate several non-ideal effects such as signal delay, powerdissipation and crosstalk that limit the overall system performance. Owing tograving effect of interconnects on the performance parameters in ICs, researchinto interconnects has become meticulously very active in recent years, and concurrentlymuch progress has been made. In the present work contemporary advancementson conventional aluminum, copper and subsequent performance analysisof next-generation graphene interconnects have been systematically performed.In compact and portable e-systems, demand for ultra low power applicationshas become very high. Subthreshold region of operation is one of the most efficienttechniques to attain low power in circuits and systems. The performanceof graphene interconnects at subthreshold region and its future scope have beenmeticulously explored in the present work.The advanced graphene on-chip interconnects have been considered for theperformance analysis. The technology node considered is 22nm. It is analyzedthat graphene based MLGNR interconnects possess better performance over copperinterconnects. It is also seen that subthreshold region of operation leads tosignificant lower power dissipation than in linear region. Power saving withsubthreshold region of operation in case of conventional copper and advancedgraphene interconnects are nearly 22% and 26% respectively. The various proposedFDTD modeling for subthreshold region is highly accurate with respect toSPICE simulation results. The maximum percentage error is less than 3%.viAt miniaturized technology nodes, variation due to temperature, fabricationprocess and environmental fluctuations crops up significantly that varies the systemoutput in on-chip ICs. As a result, variability analysis of on-chip interconnectsat nano regime in subthreshold region has become need of the hour. Variabilityanalysis of graphene interconnect in subthreshold region is presented. Processcorner, parametric and Monte-Carlo analyses have been performed to determinevariability effect in on-chip multilayer graphene nanoribbon (MLGNR) interconnects.
- M Tech Dissertations