Design and Implementation of Low Power Superscalar Processors

Abstract

This thesis presents an 8-stage low power Superscalar processor. Since there has come an upper limit on the frequency that a single core inline processor can provide, to improve performance we need to exploit concepts like deeper pipelining and Instruction Level Parallelism (ILP). Parallel execution of a number of instructions gives better performance. But, to achieve low power at the same time along with higher performance is a challenge. The superscalar processor in this work is designed with 8 stages as a 2-way processor, which allows at a time 2 instructions to run and complete in parallel. The processor has been designed using Verilog HDL. Front-End analysis for the same has been done with the help of Cadence RTL Encounter Compiler. To achieve low power, clock gating has been applied. The library used for implementing the RTL is NLDM 45nm Nangate library. The frequency at which the designed processor worked fine is 200 MHz with the total power consumption found to be 51.5 mW.