FPGA implementation of an improved proportionate normalized least mean square (IPNLMS) algorithm

Abstract

In digital signal processing, estimation of an unknown signal is an important task,and in this context, different type of adaptive filters has been proposed to identifythese systems for on-line applications. Adaptive filters update its weight withthe help of certain algorithms. For real-time application, however, it is necessaryto implement these algorithms in hardware using the different basic mechanismof VLSI. Some algorithms with low computational complexity, like LMS, NLMShave been successfully implemented on FPGA.In this thesis, a popular sparse adaptive algorithm called IPNLMS algorithm,has been implemented on FPGA, Spartan 3E. In particular, on that FPGA board,we have designed 4-tap IPNLMS algorithm with maximum achievable frequencyof 21.85 MHz. Furthermore, this thesis proposes an architecture for 128-tapsIPNLMS algorithm, which is finally simulated on ISE design suite of Xilinx tool.The main feature of the proposed architecture is that it include minimum delay,and matrix multiplication is performed using minimum arithmetic operations,and scalar division has been implemented with suitable LUTs. It has also beenshown that the architecture is working at the frequency 40 MHz.