Design and implementation of a low power superscalar processor

Abstract

Designed and Implemented a Superscalar processor, where it fetches and issues two instructions simultaneously and it has 6 stages. Initially, concentrated on designing the architecture to make the processor executing multiple instructions simultaneously. The architecture has separate memories for both instruction and data so that there will be no problem of overlapping of data when accessing the memory for fetching the instructions and executing the memory instructions i.e., avoiding structural hazard and the architecture is implemented using verilog which is a Hardware Description Language. Now, a 1-bit branch predictor is added to the design to decrease the branch penalty which will effect the processor performance and it is used to avoid control hazards. After that, load balancing of pipeline stages is done to improve the processor performance using Cadence RTL Compiler, which will make all the stages to work with almost same frequency and same slack and Nangate 45nm fast library is used for synthesis. Later, clock gating and power gating technique is done using CPF (Common Power Format) file which will try to reduce the power consumed. Finally, Back-end analysis is done using Cadence SoC encounter tool and tried to reduce the timing violations