Design and implementation of low power superscalar processor

Abstract

This thesis presents design of a low power, general purpose, 4 issue superscalar processor, which fetches 4 instructions simultaneously and executes them parallelly. The processor fetches the instruction in program order, executes them out of order and again writes the result back in their correct program order. To perform the out of order execution Tomasulo 's algorithm is being used in the design. As it is general purpose processor, all the reservation stations, queues and buffers are designed to be general to speed up the execution. Work is equally being distributed among different stages using load-balancing to enhance the performance of the processor. Low power constraints like clock-gating, power-gating, max flops, min flops, maximum fanouts etc. are applied to make the design low power. Implementation is being done on the cadence tools- RTL compiler and Encounter. Design is working efficiently for all the test cases at 500MHZ with the slack of 121ps and power of 57.17mW.