| dc.description.abstract | Radio frequency design has been one of the major research areas in the recent past. Emergence of several Wireless Communication standards has demanded availability of different analog blocks for use in transceivers with different constraints, imposed by the nature of application. Particularly, lot of research has been carried out in CMOS technology, due to its low cost nature.
LNA is one of the most important building blocks in the front end of the wireless communication systems. It determines the noise performance of the overall system, as it is the first block after the antenna. With technology scaling, the transistor’s cut off frequency continues to increase, which is desirable for improving the noise performance of CMOS circuit. Some other advantages like low cost, high level of integration motivates research of RF modules using CMOS technology. In recent years valuable research is done on CMOS LNA design in submicron technologies: from topology investigation to various new ideas on improvement of low power consumption, low noise figure, high gain, smaller space and low supply voltage.
In this thesis, a new LNA architecture is reported, that consumes less power compared to other existing architectures, while providing the same gain, noise figure, CP-1dB and IIP3 figures. The new architecture achieves this better performance by combining the beneficial properties of two existing architectures – Lee’s inductive input stage, and the current-reuse (or the CMOS inverter amplifier) architecture. Detailed design procedures, and Spice simulation results are presented in the thesis, along with a brief survey of noise sources in MOSFETs, and a literature survey of existing LNA architectures. | |
