Design and implementation of low power processor design using RISC-V ISA

Abstract

This thesis, represents a design in which the processor is made to work once or twice on occurrence of external signal, therefore the processor remains idle most of the time. Unlike the processor used in mobile phones, laptops, it wakes up only when an interrupt comes either from the outside devices or sensors which are assign with a specific program called interrupt handler. The interrupt controller transmits the interrupt to the processor on priority basis, based on which processor suspends its current existing task and serve the interrupt. Interrupt controller communicate with processor via bus architecture and sends the interrupt. Processor are not meant to run user-based program. These processors run on battery, therefore they should be energy efficient.The design of a processor comprises of three stages, which is running at 10MHz of frequency. The lower number of stages constitutes less hardware, since there will be no stalls due to data-dependency, hence low power. The arbiter buffers the interrupts coming from external devices to the processor via bus, which runs at 200KHz of frequency.To have less power in the design, there are various power reduction techniques followed during synthesis process like clock gating, MSV technique, using high Vt cells and using high fan-in cells. All these techniques though increase the hardware but will also reduce the (dynamic, static, short circuit) power consumption by a significant amount. Lowering of the power helps to reduce heat dissipation in the chip. Along with the power reduction techniques, there are various other files used in the scripting language during synthesizing like HDL files, SDC file, TCF file, CPF file and many attributes.