Physical design implementation of “ARP Block-4” module at 28nm “CHIPTOP” module at 90nm
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VLSI design flow from RTL to GDSII consists of two phases, namely front-end design and back-end design. The physical design is the process of transforming a circuit description into the physical layout, which describes the position of cells and routes for the interconnections between them. Figure 1 shows a schematic representation of a layout. The main concern in the physical design of VLSI-chips is to find a layout with minimal area, further the total wire-length has to be minimized. For some critical nets there are hard limitations for the maximal wire-length. Due to its complexity, the physical design is normally broken in various sub-steps: 1) First the circuit has to be partitioned to generate some macro cells. 2) In the floorplanning phase the cells have to be placed on the layout surface. 3) After placement the global routing has to be done. In this step the `loose' routes for the interconnections between the single modules (macro cells) are determined. 4) In the detailed routing the exact routes for the interconnection wires in the channels between the macro cells have to be computed. 5) The last step in the physical design is the compaction of the layout, where it is compressed in all dimensions so that the total area is reduced. This classical approach of the physical design is strongly serial with many inter-dependencies between the sub-steps. For example during floorplanning and global routing there must be enough routing space reserved to complete the exact wiring in the detailed routing phase. Otherwise the placement has to be corrected and the global routing has to be computed again. In this project, back-end design (PnR) is done on two modules namely ChipTop at 90nm technology node and ARP Block4 at 28nm technology node. Physical Design is done with help of EDA tool Synopsys IC Compiler. EDA tools provide the design automations for IC design process which can reduce the design TAT. In order to reduce the design cost, the chip-area is reduced as small as possible. Reports at each stage of physical design are analysed. any congestion removal techniques are applied to remove congestion from ARP Block4 and improve timing.
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