Full chip interface timing, pipeline planning and rapid floorplanning

Abstract

This report gives some glance on VLSI design flow and mainly deals with Physical Design of the chip. This is a very important step of the flow because it decides the shape and size of the chip. This step ensures that the area is as minimum as possible and also it has the optimum delay. It also makes sure that while optimizing area, the functionality of the design is not affected. The main focus of the project was on full chip interface timing to plan how many pipeline stages needs to be added in the design to meet the timing requirements and on initial automatic floorplanning as an early step towards the final floorplan. The EDA tools used to accomplish the task were Prime Time from Synopsys and Innovus from Cadence and most of the scripting is done in Tcl/Tk