Design of low power interrupt driven RISC-V instruction set processor for embedded systems
This thesis presents a design for low power, interrupt driven processor compatible with RISC-V Instruction Set Architecture (ISA). The processor is designed to target the application of home automation systems. To accomplish low power objectives,algorithm is designed to support low power modes with power aware design for occasional interrupts to the processor. The proposed algorithm for low power design, is mainly working for two low power modes, normal sleep mode and deep sleep mode. The Platform Level Interrupt Controller (PLIC) design is governed by an algorithm that can decide to control the state of 5-stage pipelined RISC-V ISA compatible processor based on the priority of available Interrupt requests (IRQs). The PLIC has five different working modes, Reset mode, NMI (Non-maskable Interrupt) mode, Vector table initialization mode, Interrupts Enable/ Disable mode and Normal ISR execution mode. Low power constraints are applied to make a low power processor that will handle the interrupt requests coming from theWake-up Interrupt Controller (WIC). It is designed to handle the low power modes as per the request made by PLIC. A bus and peripheral bridge are also designed to transfers data between the processor and Synchronous Serial Ports (SSPs) running at different frequencies. The processor has been microarchitected,simulated using Verilog and synthesized with different 45nm and 180nm technology nodes for Application Specific Integrated Circuit (ASIC).
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